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| CD4035BMS December 1992 CMOS 4 -Stage Parallel In/Parallel Out Shift Register Description CD4035BMS is a four stage clocked signal serial register with provision for synchronous PARALLEL inputs to each stage and SERIAL inputs to the first stage via JK logic. Register stages 2, 3, and 4 are coupled in a serial D flip-flop configuration when the register is in the serial mode (PARALLEL/SERIAL control low). Parallel entry into each register stage is permitted when the PARALLEL/SERIAL control is high. In the parallel or serial mode information is transferred on positive clock transitions. When the TRUE/COMPLEMENT control is high, the true contents of the register are available at the output terminals. When the TRUE/COMPLEMENT control is low, the outputs are the complements of the data in the register. The TRUE/ COMPLEMENT control functions asynchronously with respect to the CLOCK signal. JK input logic is provided on the first stage SERIAL input to minimize logic requirements particularly in counting and sequence-generation applications. With JK inputs connected together, the first stage becomes a D flip-flop. An asynchronous common, RESET is also provided. The CD4035BMS series type is supplied in these 16 lead outline packages Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H1F H6W Features * J - K Serial Inputs and True/Complement Outputs * High Voltage Type (20V Rating) * 4-Stage Clocked Shift Operation * Synchronous Parallel Entry on All 4 Stages * JK Inputs on First Stage * Asynchronous True/Complement Control on All Outputs * Static Flip-Flop Operation; Master-Slave Configuration * Buffered Inputs and Outputs * High Speed Operation 12MHz (Typ) at VDD = 10V * 100% Tested for Quiescent Current at 20V * Standardized, Symmetrical Output Characteristics * 5V, 10V and 15V Parametric Ratings * Meets All Requirements of JEDEC Tentative Standard Number 13A, "Standard Specifications for Description of `B' Series CMOS Devices" Applications * Counters, Registers - Arithmetic-Unit Registers - Shift Left/Shift Right Registers - Serial-to-Parallel/Parallel-to-Serial Conversions * Sequence Generation * Control Circuits * Code Conversion Pinout CD4035BMS TOP VIEW Functional Diagram PARALLEL IN 9 1 10 2 11 3 12 4 CL FIRST STAGE TRUTH TABLE tn-1 (INPUT) J 0 1 K X X 0 0 R 0 0 0 0 Qn-1 0 0 1 Qn-1 tn (OUTPUT) Qn 0 1 0 Qn-1 Toggle Mode 1 Qn-1 0 Q1/Q1 1 TRUE/ COMP. 2 K3 J4 RESET 5 CLOCK 6 P/S 7 VSS 8 16 VDD 15 Q2/Q2 14 Q3/Q3 13 Q4/Q4 12 PI-4 11 PI-3 10 PI-2 9 PI-1 SER IN J K P/S T/C 4 3 6 7 2 5 1 15 14 13 4-STAGE REGISTER CLK X 1 RESET VDD = 16 VSS = 8 X X 1 X X 0 0 1 1 Qn-1 X Q1/Q1 Q2/Q2 Q3/Q3 Q4/Q4 T/C OUT X X CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999 File Number 3308 7-851 Specifications CD4035BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, +25oC, LIMITS TEMPERATURE +25oC +125 oC PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND MIN -100 -1000 -100 - MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V -55oC +25 C +125oC -55oC +25oC +125oC -55oC +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +125oC, -55oC -55oC o - +25oC, +125oC, -55oC 14.95 0.53 1.4 3.5 -2.8 0.7 VOH > VOL < VDD/2 VDD/2 3.5 11 1.5 4 - V V V V +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 7-852 Specifications CD4035BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN 2 1.48 MAX 500 675 460 621 200 270 UNITS ns ns ns ns ns ns MHz MHz PARAMETER Propagation Delay Clock to Q Propagation Delay Reset to Q Transition Time SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TTHL TTLH FCL CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND Maximum Clock Input Frequency NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55oC Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 3 mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V MIN MAX 5 150 10 300 10 600 50 UNITS A A A A A A mV 7-853 Specifications CD4035BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Input Voltage High Propagation Delay Clock to Q Propagation Delay Reset tO Q Transition Time SYMBOL VIH TPHL1 TPLH1 TPHL2 TPLH2 TTHL TTLH TW CONDITIONS VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Maximum Clock Input Frequency Maximum Clock Rise and Fall Time (Note 4) FCL VDD = 10V VDD = 15V TRCL TFCL VDD = 5V VDD = 10V VDD = 15V Minimum Data Setup Time J/K Lines Minimum Data Setup Time Parallel-In Lines Minimum Clock Pulse Width TS VDD = 5V VDD = 10V VDD = 15V TS VDD = 5V VDD = 10V VDD = 15V TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded, tRCL should be made less than or equal to the sum of the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta SYMBOL IDD VNTH VTN VTP VTP CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 TEMPERATURE +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 MAX 25 -0.2 1 2.8 1 UNITS A V V V V CIN Any Input NOTES 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC, +125oC, -55oC +25oC +25o C +25oC +25 oC o MIN 7 6 8 - MAX 200 150 200 160 100 80 250 110 40 15 15 15 220 80 60 140 50 40 200 90 60 7.5 UNITS V ns ns ns ns ns ns ns ns ns MHz MHz s s s ns ns ns ns ns ns ns ns ns pF +25 C +25oC +25 C +25 C +25oC +25oC +25 C +25oC +25 oC o o o Minimum Reset Pulse Width +25oC +25oC +25oC +25 C +25oC +25oC +25oC +25oC +25 C +25oC +25oC o o 7-854 Specifications CD4035BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Functional SYMBOL F CONDITIONS VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1 TEMPERATURE +25oC MIN VOH > VDD/2 MAX VOL < VDD/2 1.35 x +25oC Limit UNITS V ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 1.0A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. 5% parametric, 3% functional; cumulative for static 1 and 2. MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 OPEN 1, 13 - 15 1, 13 - 15 1, 3, 4 1, 13 - 15 GROUND 2 - 12 8 2, 5, 7 - 12 8 VDD 16 2 - 7, 9 - 12, 16 16 2 - 7, 9 - 12, 16 13 - 15 6 9V -0.5V 50kHz 25kHz 7-855 Specifications CD4035BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN GROUND VDD 9V -0.5V 50kHz 25kHz Logic Diagram * 9 * 10 * 11 * 12 *ALL INPUTS PROTECTED BY CMOS INPUT PROTECTION NETWORK VDD * 4 J * 3 K D P Q D P Q D P Q D P Q * 5 RESET CL Q CL Q PS R R R CL Q PS R CL Q PS VSS * 6 CLOCK PS * 7 PARALLEL/ SERIAL CONTROL T p n T T T p n T T p n T T p n T T p n T T p n T T p n T T p n T T * 2 TRUE/COMPLEMENT P/S = 0 = SERIAL MODE T/C = 1= TRUE OUTPUTS P D Q P 1 Q1/Q1 PS p n PS D p n PS PS CL CL p n CL CL p n CL R CL p n CL 15 Q2/Q2 14 Q3/Q3 13 Q4/Q4 Q Q R CL Q PS CL p n CL PS PS CL CL FIGURE 1. TYPICAL STAGE DETAIL LOGIC 7-856 CD4035BMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) 30 25 20 15 10 5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V 10V 5V 0 5 10 15 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 1 . TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 2. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0 0 -5 -10 -15 0 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 100 -10V -20 -25 -10V -10 -15V -30 -15V -15 FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPHL, tPLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC CLOCKED OPERATION 300 200 SUPPLY VOLTAGE (VDD) = 5V 150 200 SUPPLY VOLTAGE (VDD) = 5V 100 10V 50 15V 10V 100 15V 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 0 20 40 60 80 LOAD CAPACITANCE (CL) (pF) FIGURE 5. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (Q OUTPUT) 7-857 CD4035BMS Typical Performance Characteristics (Continued) MAXIMUM CLOCK INPUT FREQUENCY (fCL) (MHz) AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (CL) = 50PF 15 POWER DISSIPATION PER GATE (PD) (W) 20 106 8 6 4 2 AMBIENT TEMPERATURE (TA) = +25oC 105 8 6 4 SUPPLY VOLTAGE (VDD) = 15V 10 104 2 8 6 4 2 10V 10V 5V CL = 50pF CL = 15pF 2 4 68 2 4 68 2 4 68 2 4 68 2 4 68 5 103 8 6 4 2 0 0 5 10 15 20 SUPPLY VOLTAGE (VDD) (V) 102 1 103 10 102 INPUT FREQUENCY (fI) (kHz) 104 FIGURE 7. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK INPUT FREQUENCY 9 LEFT/RIGHT RIGHT SHIFT INPUT CLK T/C RESET LEFT SHIFT OUTPUT 7 4 3 6 2 5 P/S J K CL T/C R Q1 1 PI-1 10 PI-2 11 PI-3 12 PI-4 LEFT SHIFT INPUT Q1 Q2 Q3 Q4 P/S CARRY FORWARD Q2 15 Q3 14 Q4 13 RIGHT SHIFT OUTPUT VDD PI-2 TRUE/COMP CONTROL IN TRUE MODE PI-3 FIGURE 9. SHIFT LEFT/SHIFT RIGHT REGISTER PI-4 Using Couleur's Technique (BIDEC)*, a binary number (most significant bit, MSB) first is shifted and processed, such that the BCD equivalent is obtained when the last binary bit is clocked into the register. The CD4035BMS, with the correct conversion logic, can also be used as a BCD-to-binary converter. *NOTE: The basic rule is: If a 4 or less is in a decade, shift with the next clock pulse; if a 5 or greater is in a decade, add 3 and then shift at the next clock pulse. For more information refer to "IRE TRANSACTIONS ON ELECTRONIC COMPUTERS", Dec. 1958, pages 313-316. FIGURE 10. BIDEC LOGIC 7-858 CD4035BMS VDD 9 7 2 6 4 3 5 P/S T/C CL J K R Q1 1 Q2 15 Q3 14 Q4 13 PI-1 10 PI-2 11 PI-3 12 PI-4 Control = E = 0 Q1 A 0 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 Q2 B 0 0 1 0 1 0 0 1 1 0 1 1 1 0 0 Q3 C 0 0 0 1 0 1 0 0 1 1 0 1 1 1 0 Q4 D 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 15 14 13 10 5 11 6 12 9 2 4 8 1 3 7 Q1 A 1 0 1 0 1 1 0 0 1 0 0 0 1 1 1 1 Q2 B 1 1 0 1 0 1 1 0 0 1 0 0 0 1 1 Q3 C 1 1 1 0 1 0 1 1 0 0 1 0 0 0 1 Q4 D 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 4 STAGE REGISTER 1 2 5 10 4 2345 1/2 CD4012 1 9 2345 CD4002 1/2 1 "E" CONTROL 3 6 13 9,10 11,12 CD4002 1/2 13 9,10 11,12 1/2 CD4012 13 1 3 1 2 1/2 CD4030 11 7 14 12 8 5 1/2 4 CD4030 6 Using a control line (E) two different state sequences can be generated. For example, suppose the following two sequences are desired on command (control line E). FIGURE 11(b). STATE SEQUENCES FIGURE 11(a). DOUBLE SEQUENCE GENERATOR 9 7 CLOCK CARRY INPUT VDD RESET 6 4 3 2 5 P/S CL J K T/C R Q1 1 PI-1 10 PI-2 11 PI-3 12 PI-4 7 6 4 P/S CL J K T/C R 9 PI-1 10 PI-2 11 PI-3 12 PI-4 UNITS REGISTER VDD Q2 15 Q3 14 Q4 13 BCD UNITS OUT 3 2 5 TENS REGISTER Q1 1 Q2 15 Q3 14 Q4 13 BCD TENS OUT P/S BCD UNITS (BIDEC LOGIC) FIG 7 PI-2 TO UNITS REGISTER PI-3 PI-4 CARRY FORWARD P/S BCD TENS (BIDEC LOGIC) FIG 7 PI-2 CARRY FORWARD TO NEXT DECADE TO TENS REGISTER PI-3 PI-4 FIGURE 12. BINARY-TO-BCD CONVERTER 7-859 CD4035BMS Chip Dimensions and Pad Layout Dimensions in parantheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: Thickness: 11kA - 14kA, PASSIVATION: 10.4kA - 15.6kA, Silane AL. BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 860 |
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